LVDS SERDES Transmitter / Receiver IP Cores User Guide

Download PDF
ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.5.3.2. Resetting the DPA

When the data becomes corrupted, you must reset the DPA circuitry using the rx_reset port and rx_fifo_reset port.

Assert the rx_reset port to reset the entire DPA block. This requires the DPA to be trained before it is ready for data capture.

Note: Intel recommends using the option to automatically reset the bit serial FIFO when the rx_dpa_locked signal rises for the first time, if available for your device family; otherwise, toggle the rx_fifo_reset port after rx_dpa_locked is asserted. This option ensures the synchronization FIFO is set with the optimal timing to transfer data between the DPA and high-speed LVDS clock domains.

Assert the rx_fifo_reset port to reset only the synchronization FIFO. This allows you to continue system operation without having to re-train the DPA. Using this port can fix data corruption because it resets the FIFO; however, it does not reset the DPA circuit. In Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, the rx_dpa_locked port remains in its previous state; if it was deasserted, it remains deasserted and you are not be able to use it to know when the DPA is using the ideal phase tap for data capture.

When the DPA is locked, the ALTLVDS block is ready to capture data. The DPA finds the optimal sample location to capture each bit. The next step is to set up the word boundary using custom logic to control the rx_channel_data_align port on a channel-by-channel basis.

The word aligner or the bit-slip circuit can be reset using the rx_cda_reset port. This circuit can be reset anytime and is not dependent on the PLL or DPA circuit operation.

Level Two Title