Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
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Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Secure Device Manager (SDM) Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Note: The Intel® Stratix® 10 GX 10M device has two independent SDM, one for each die.
Table 13.  SDM Pins (See Note 11)
Pin Name ( Intel® Stratix® 10 Devices) Pin Name ( Intel® Stratix® 10 GX 10M Device) Pin Description MSEL[2:0] Pin Functions Connection Guidelines
RREF_SDM

F1_RREF_SDM

F2_RREF_SDM

Reference resistor input for the PLLs of the SDM interface.

 — Input

Connect a 2kΩ +/-1% resistor to GND.
SDM_IO0 F[1,2]_SDM_IO0

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO1 F[1,2]_SDM_IO1

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA2 Connect this pin to the data2 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
3'b001 or 3'b011 AS_DATA1 Connect this pin to the data1 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO2 F[1,2]_SDM_IO2

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA0 Connect this pin to the data0 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
3'b001 or 3'b011 AS_CLK Connect this pin to the clock input of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO3 F[1,2]_SDM_IO3

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA3 Connect this pin to the data3 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
3'b001 or 3'b011 AS_DATA2 Connect this pin to the data2 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO4 F[1,2]_SDM_IO4

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA1 Connect this pin to the data1 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
3'b001 or 3'b011 AS_DATA0 Connect this pin to the data0 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO5 F[1,2]_SDM_IO5

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[0] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel® Stratix® 10 Configuration User Guide.

— MSEL[0] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO0 Connect this pin to the nCS input of the first QSPI flash device when configuring from QSPI flash devices.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO6 F[1,2]_SDM_IO6

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA4 Connect this pin to the data4 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
3'b001 or 3'b011 AS_DATA3 Connect this pin to the data3 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO7 F[1,2]_SDM_IO7

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[1] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel® Stratix® 10 Configuration User Guide.

— MSEL[1] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO2 Connect this pin to the nCS input of the third QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO8 F[1,2]_SDM_IO8

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_READY Connect this pin to the ready signal output of the external configuration controller when configuring using the Avalon-ST x8, x16, or x32 interface.
3'b001 or 3'b011 AS_nCSO3 Connect this pin to the nCS input of the fourth QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO9 F[1,2]_SDM_IO9

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[2] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel® Stratix® 10 Configuration User Guide.

— MSEL[2] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO1 Connect this pin to the nCS input of the second QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO10 F[1,2]_SDM_IO10

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA7 Connect this pin to the data7 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO11 F[1,2]_SDM_IO11

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_VALID Connect this pin to the data valid pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO12 F[1,2]_SDM_IO12

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

— Any MSEL setting The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO13 F[1,2]_SDM_IO13

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA5 Connect this pin to the data5 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO14 F[1,2]_SDM_IO14

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_CLK Connect this pin to the clock output of an external configuration controller when configuring using the Avalon-ST x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO15 F[1,2]_SDM_IO15

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

 3'b110 AVSTx8_DATA6 Connect this pin to the data6 pin of an external configuration controller when configuring using the Avalon-ST x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO16 F[1,2]_SDM_IO16

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
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