Intel® FPGA Schematic Review Worksheets
Intel® FPGA provides schematic review worksheets intended to help you review your schematic and adhere to Intel's guidelines. These worksheets are based on the respective device Pin Connection Guidelines and other referenced Intel FPGA documentation applicable to board-level pin connections that need to be considered when you finalize your schematic. The schematic review worksheets are linked in the below tables to download in Microsoft* Office Word document format.
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For information on boundary-scan testing, refer to the Intel BSDL Support page.