Description
You may see this error in the Intel® Quartus® Prime Pro Edition Software v21.3 and earlier when using IOPLLs in Banks 3C and 3D in Intel Agilex® 7 F-Series SoC FPGA devices.
The error occurs because the HPS Shared GPIO Banks (3C & 3D) do not support IOPLLs in Normal and Source Synchronous compensation modes.
Resolution
If the IOPLL needs to operate in Normal or Source Synchronous modes, select a location that is not adjacent to the HPS Bank. Alternatively, choose another IOPLL compensation mode.
This information will be added to a future release of the Intel Agilex® 7 FPGA Clocking and PLL User Guide.