For Qsys designs that include a Triple Speed Ethernet (TSE) MegaCore function and target the Cyclone IV GX device family, Synopsys Design Constraint Files (.sdc) generated by Qsys contain the following warning:
Warning: ignored filter at altera_reset_controller.sdc(17): *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr
could not be matched with a pin
This warning does not pertain to the Cyclone IV GX device family and is generated in error. You may safely ignore this warning.