Due to a problem with Intel® Quartus® Prime software version 17.1 and earlier, the Altera® PLL may fail to switch the reference clock input when using the Manual Switchover mode in Arria® V, Cyclone® V and Stratix® V devices. When this problem occurs, Altera PLL always selects one of two reference clocks regardless of the status of extswitch signal.
You can know whether this problem occurs or not from fitter report. See PLL Refclk Select under PLL Usage Summary in fitter report. There are PLL Reference Clock Input 0 source and PLL Reference Clock Input 1 source. If the problem occurs, the same clock signal is connected to both of them incorrectly. If the problem doesn't occur, two different clock signals are connected to them respectively.
Changing the locations of two reference clock input pins may work around this problem :
- Exchange two reference clock input pin locations
- (Example) When connecting clock_a signal to clk0 input and clock_b signal to clk1 input currently, connect clock_a signal to clk1 input and clock_b signal to clk0 input
- Change one or both of two reference clock input pin locations
- (Example) When connecting clock_a signal to clk0 input and clock_b signal to clk1 input currently, connect clock_b siganl to clk3 input
If these workarounds do not improve the problem or you can't change the reference clock input pin locations, file a Service Request through mySupport.