Article ID: 000086659 Content Type: Troubleshooting Last Reviewed: 08/25/2023

Why is the Configuration via Protocol (CvP) periphery image configuration time exceeding the PCIe 100 ms power-up-to-active time requirement?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In Intel® Quartus® Prime Pro Edition Software version 21.2, the CvP PCIe link might not be able to enumerate properly with Intel Agilex® 7 devices. This is because the periphery image configuration time exceeds the PCIe 100 ms power-up-to-active time requirement.

    Resolution

    To work around this problem, re-enumerate the PCIe link once the FPGA is successfully configured.

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series