Why does my design that uses a corner clock pin to drive a corner PLL...

Environment

FPGA Intellectual Property

PLL

Description

Due to a problem in the Quartus® II software versions 10.0 and earlier, a design using a corner clock pin to drive the corner PLL on a Stratix® III device may not function as intended because timing analysis on the path from the corner clock pin to the PLL is incorrect. Timing paths in your design involving the corner clock pin and the corner PLL may fail due to unmet timing requirements even if no violations are reported by the TimeQuest timing analyzer.

This problem may affect your design only if the corner clock pin drives the corner PLL. In particular, the problem affects Stratix III 3S200, 3S260, and 3S340 devices. However, the problem does not affect these devices in the H780, F1152, and H1152 packages because there are no corner PLLs in these packages. Other Stratix III devices and devices from other device families are not affected.

If your Stratix III design is working as expected, no action is needed.

If you are seeing failures on your Stratix III design or if you are compiling a new Stratix III design using the Quartus II software versions 10.0 or earlier, download and install the Quartus II software patch from the appropriate links below.