Article ID: 000086205 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 14.1.

    Related Products

    This article applies to 13 products

    Stratix® V GT FPGA
    Arria® V GZ FPGA
    Cyclone® V GX FPGA
    Arria® V GT FPGA
    Stratix® V E FPGA
    Arria® V ST SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Stratix® V GX FPGA
    Arria® V SX SoC FPGA
    Arria® V GX FPGA
    Stratix® V GS FPGA
    Cyclone® V GT FPGA