Description
Yes, there is an error with Figure 2-12. CLK[11..8] pins feed PLL3 and PLL3 feeds the top clock control block. CLK[15..12] pins feed PLL4 and PLL4 feeds the
bottom clock control block.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
bottom clock control block.
The figure incorrectly shows that the left and right clock control blocks feed PLL3 and PLL4, respectively. The figure below shows the correct connections.
Figure 2-12. EP2C20 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations
![Figure 2-12. EP2C20 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations](http://www.altera.com/support/kdb/images/rd01112005_169_fig1.gif)
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.