Article ID: 000085612 Content Type: Troubleshooting Last Reviewed: 04/08/2014

Why does the tx_datak signal refer to received data for the Arria V, Cyclone V and Stratix V devices in the Altera Transceiver PHY IP User Guide?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to mistakes in "Table 9-12: Avalon-ST TX Interface Signals" and "Table 11-8: Avalon-ST TX Interface" of the Altera® Transceiver PHY IP Core User Guide (PDF) the tx_datak signal refers to received data for the Arria® V, Cyclone® V and Stratix® V devices.

    The tx_datak signal should only refer to the transmit data.

    Resolution

    These problems will be fixed in a future version of the Altera Transceiver PHY IP Core User Guide (PDF).

    Related Products

    This article applies to 12 products

    Cyclone® V ST SoC FPGA
    Cyclone® V GX FPGA
    Cyclone® V SX SoC FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Cyclone® V GT FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GZ FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Stratix® V GX FPGA

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