Description
There might be cases where the PLL is fully powered up, but the input clock has not started toggling yet. If this is the case in your system, once the input clock starts toggling, assert ARESET for 10ns and then allow the PLL to lock onto the input clock. This will guarantee that all the clock outputs from the PLL will have the correct phase after the PLL locks onto the input clock.
Environment
PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT