Article ID: 000083331 Content Type: Troubleshooting Last Reviewed: 11/27/2013

Why does the Altera PLL fail to lock in simulation after installing the dp5 patch?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Altera® PLL simulation model may fail to operate correctly and fail to assert the locked signal after installing the dp5 patch for version 13.0sp1 of the Quartus® II software.

    You will see this problem if you are simulating a PLL using Dynamic Phase Stepping or Dynamic Reconfiguration.

    The problem is with the simulation model, so does not affect the operation of the PLL when implemented in hardware.

    Resolution This problem is resolved in version 13.1 of the Quartus II software.

    Related Products

    This article applies to 15 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA