Critical Issue
This problem affects DDR2, DDR3, QDR II, and RLDRAM II products.
Error messages similar to the following may occur when running post-fit simulation of VHDL designs:
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(32614):
(vcom-1136) Unknown identifier "test_mode".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(32615):
(vcom-1136) Unknown identifier "use_duty_cycle_correction".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(71612):
(vcom-1035) Formal port "clkin" has OPEN or no actual associated
with it.
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(183112):
(vcom-1136) Unknown identifier "test_mode".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(183113):
(vcom-1136) Unknown identifier "use_duty_cycle_correction".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(225095):
(vcom-1136) Unknown identifier "test_mode".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(225096):
(vcom-1136) Unknown identifier "use_duty_cycle_correction".
# ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(237040):
VHDL Compiler exiting
.
The workaround for this issue is to modify the post-fit netlist, as follows:
- Open the post-fit netlist file <core_name>.vho in a text editor.
- Locate and remove the following parameter declaration for stratixv_leveling_delay_chain:
test_mode => "false"
use_duty_cycle_correction => "false"�
- Ground the
clkin
port ofstratixv_pll_dll_output
:
clkin => "0000"
- Ground the
tdoutap
port ofstratixv_jtag
:
tdoutap -> ‘0’
This issue will be fixed in a future version.