Article ID: 000082824 Content Type: Error Messages Last Reviewed: 02/16/2023

Error(175020): The Fitter cannot place logic pin that is part of pcie_example_design pcie_example_design in region (95, 2) to (95, 2), to which it is constrained, because there are no valid locations in the region for logic of this type

Environment

  • Intel® Quartus® Prime Pro Edition
  • QSYS Example Designs
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When you compile the Intel® Stratix® 10 Hard IP for PCI* Express MX H-Tile ES1 FPGA Devkit Design Example with any feature enabled in the Configuration, Debug, and Extension Options tab via the Intel® Stratix® 10 PCIe* IP Parameter Editor, you may see  the following Fitter error messages:

    Error(175020): The Fitter cannot place logic pin that is part of pcie_example_design pcie_example_design in region (95, 2) to (95, 2), to which it is constrained, because there are no valid locations in the region for logic of this type.

    Error(16234): No legal location could be found out of 1 considered location(s).

    Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) .

    Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).

    Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments.

     

    The Fitter error messages are due to the invalid reconfiguration clock pin location assignments in the Intel® Stratix® 10 Hard IP for PCI Express MX H-Tile ES1 FPGA Devkit Design Example.

    Resolution

    To work around this problem, change the reconfiguration clock pin locations as shown below:

     

    When switching pin location assignments in Intel® Quartus® Prime Pin Planner, reassign reconfig_clk_in_clk pins from PIN_AR26 / PIN_AP26(n) to PIN_AT13 / PIN_AU13(n). 

    When switching pin location assignments in the QSF file, make the following assignment changes:

    From pin location assignments:

    set_location_assignment PIN_AR26 -to reconfig_clk_in_clk

    set_location_assignment PIN_AP26 -to "reconfig_clk_in_clk(n)"

     

    To pin location assignments:

    set_location_assignment PIN_AT13 -to reconfig_clk_in_clk

    set_location_assignment PIN_AU13 -to "reconfig_clk_in_clk(n)"

     

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 19.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA