Due to a problem with the LDPC Intel® FPGA IP in Intel® Quartus® Prime Pro Edition Software version 17.1 targetting Intel® Stratix® 10, you may observe the above error when compiling the simulation design example generated by the IP configured with WiMedia 1.5 standard and encoder mode in Modelsim.
To work around this problem, comment out the following lines in the msim_setup.tcl:
1. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_pkg.sv" -work work
2. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_wimedia_enc.sv" -work work