Article ID: 000081845 Content Type: Error Messages Last Reviewed: 12/11/2013

Error (11924): Bank has conflicting VCCIO settings

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1, you will see this error message when assigning a differential input or bidirectional pin in a bank where VCCIO is less than 2.5V.

     

    An example of the full error message is shown below:


    Error (11924): Bank \'8D\' has conflicting VCCIO settings
    Error (11928): \'pin_name\' with I/O standard Differential 1.5-V SSTL Class I, was constrained to be within bank \'8D\'
    Info (11929): \'1.5V\' is a valid VCCIO value
    Error (11928): \'pin_name\' with I/O standard LVDS, was constrained to be within bank \'8D\'
    Info (11929): \'2.5V\' is a valid VCCIO value
    Error (11802): Can\'t fit design in device


     

     

    Resolution

    A patch is available to fix this problem for the Quartus II software version 13.1. Download and install patch 0.07 from the following link below.

     

    Download the Quartus II software version 13.1 Patch 0.07 for Windows

    Download the Quartus II software version 13.1 Patch 0.07 for Linux  

    Readme for the Quartus II software version 13.1 Patch 0.07

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