Article ID: 000081527 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Why am I unable to select a value in the parameter editor for "Mixed Port read-During-Write for Single Input Clock RAM" when targeting MLAB memory type when either the Read Address registers or Output registers are not used?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

MLAB memory types only support a specific "Mixed Port Read-During-Write for Single Input Clock RAM" value when both the Read Address registers and Output registers are being used.

If either of these register stages are disabled then the MLAB memory will default to don't care for Mixed Port Read-During-Write operations.

Resolution

None

Related Products

This article applies to 10 products

Stratix® IV E FPGA
Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA
Arria® II GX FPGA
Stratix® V GT FPGA
Arria® II GZ FPGA