Article ID: 000081253 Content Type: Troubleshooting Last Reviewed: 05/23/2023

Why do I get illegal pin location assignment when I change the target device of the 40- and 100-Gbps Ethernet MAC and PHY Intel® FPGA IP design example?

Environment

  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When you change the target device of the 40- and 100-Gbps Ethernet MAC and PHY Intel® FPGA IP design example, you must remove all the location assignments when prompted. However, you will still encounter fitter errors for illegal pin assignments. An example error message is as follows:

        Error (171016): Can't place node "cfp_mod_lopwr" -- illegal location assignment PIN_AW37.

    This error message occurs because the design example constraints are split into two Quartus® II Settings File (.qsf) files. The first .qsf file is the main project .qsf file (<variation>_example/example_design/<match>_top_sv/<match>_top_sv.qsf). In this .qsf file you will see a reference to the second .qsf file (<variation>_example/example_design/common/common_settings_sv.qsf) as follows:

        source ../common/common_settings_sv.qsf

    This second .qsf contains all the location constraints specific to the design example development board.

    Resolution

    Remove all location constraints in the file <variation>_example/example_design/common/common_settings_sv.qsf and recompile your design.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA