Why do I see the following error when compiling the PCI Express Intel® FPGA IP in the Quartus® II software version v12.0:
Error: alt_xcvr_reconfig_0: add_fileset_file: No such file */alt_xcvr_reconfig_cpu.v
This error will be seen during the Platform Designer (formerly Qsys) generation if the transceiver reconfiguration controller is included in your Platform Designer project and you have enabled the "Create simulation model: Verilog" on the Platform Designer generation page.
To work around this problem, follow either of these steps:
- Disable simulation model generation
or - Set "Create simulation model: VHDL" on the Platform Designer generation page
or - Remove the transceiver reconfiguration module from your Platform Designer project, export the reconfiguration signals to the upper project, and add the reconfiguration controller at that level of your design.
This problem has been fixed in the Quartus II software v12.1.