Description
No, in Altera® devices the DPA circuitry keeps adjusting the phase setting unless the optional rx_dpll_hold port in the altlvds megafunction is asserted.
The rx_dpll_hold input port is useful when you know you will have a long period of static data, beyond the DPA run length specification. You can assert this port to hold the DPA on its current setting. The DPA lock signal may still toggle, it is not affected by the rx_dpll_hold port.
When the phase relationship between data and clock changes, the DPA will adjust the phase setting accordingly. The DPA is designed to maintain the optimal phase relationship between the reference clock and data across voltage and temperature variations during device operation.