Article ID: 000080570 Content Type: Troubleshooting Last Reviewed: 01/01/2015

What can cause the fPLLs to not function properly in Stratix V, Arria V, or Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The fPLLs in Stratix® V, Arria® V, and Cyclone® V devices require the RREF pin(s) to be connected to GND through a precision resistor in order to function properly.  If the RREF pin(s) are tied directly to GND or left floating, some or all of the fPLLs may fail to function.

Resolution

Refer to the Device Pin Connection Guidelines for the device you are using for specific guidance on how to connect the RREF pins. 

You can also refer to Possible Causes for PLL Loss of Lock.

 

Related Products

This article applies to 15 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Stratix® V E FPGA
Cyclone® V SX SoC FPGA
Stratix® V GX FPGA
Cyclone® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Cyclone® V ST SoC FPGA
Cyclone® V GT FPGA
Arria® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Cyclone® V SE SoC FPGA