Is there any known issue using the On-chip parallel termination (RT) with UniPHY IP ?

Yes, there is an issue with the Parallel On Chip Termination (OCT) with calibration setting in the configuration file generated by the Quartus® II software version 11.0 and 11.0 SP1. Although the parallel OCT with calibration is enabled for the specific pins in assignment editor and the setting is reflected in the compilation report, the Quartus II software does not correctly enable the configuration bits for the parallel OCT setting in the configuration file. 

This issue impacts Stratix® III and Stratix IV device families and DDR3 SDRAM, DDR2 SDRAM, RLDRAM II, QDR II/ SRAM IP cores. You may see calibration failure because of this issue.

The issue will be fixed in the next release of the Quartus II® software. To overcome this issue in Quartus II software version 11.0 and 11.0SP1, you need to install the patch given in the related solution below and perform a full compilation of your design.