Article ID: 000080394 Content Type: Troubleshooting Last Reviewed: 01/18/2023

Why does the Altera LVDS SERDES IP in Tx mode fail to generate the VHDL simulation model?

Environment

  • Intel® Quartus® Prime Pro Edition
  • LVDS SERDES Intel® FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.0 and later, you may see the Altera LVDS SERDES IP fails to generate. This problem occurs when the IP is in Tx mode, and you have selected VHDL for the simulation model. 

    Resolution

    To work around this problem, generate the simulation model in Verilog HDL.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs