Article ID: 000078075 Content Type: Troubleshooting Last Reviewed: 12/11/2015

When executing the KEY_VERIFY instruction, why are register bits related to the volatile key sometimes set after power-up, even though no key is programmed in Stratix V, Arria V or Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may observe register bits related to the volatile key sometimes being set after power-up when executing the KEY_VERIFY JTAG instruction, even though no key is programmed in Stratix® V, Arria® V or Cyclone® V devices. This is because there is no power-up reset for the registers that are powered by VCCBAT, so these bits are undefined at power-up.

This will not cause an issue with programming the key.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA