Article ID: 000077779 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get the error "Nios II generation failed, input clock is unknown or set to 0" in Qsys when generating my project in Linux?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    An issue has been identified in multi-user environments with the UniPHY DDR3 SDRAM controller in Qsys.  In an embedded system, this can result in error messages similar to the following:

    • cpu: Nios II generation failed, input clock is unknown or set to 0

    During generation, the Quartus® II software creates a directory "/tmp/compute_pll_temp" to hold temporary files regarding PLL calculations. However, this directory is not deleted on completion. The result is that if a different user then generates the core, permissions may prevent the PLL calculations being written.

    Resolution

    To work around this issue, users should delete the /tmp/compute_pll_temp directory after running the tool, or change permissions on the directory to allow all users write access.

    This issue will be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA