Article ID: 000077363 Content Type: Troubleshooting Last Reviewed: 01/31/2023

Why can't I access PCIe registers after generating Intel® Quartus® Prime Software 16.1 PCIe CvP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may not be able to access Arria® 10 PCIe® IP Core registers if the Arria 10 device uses Configuration via Protocol (CvP) mode and was generated using Quartus® Prime version 16.1, 16.1.1, and 16.1.2.

     

     

    Resolution

    To work around this issue, change the altera_pcie_a10_hip_161_*.v USE_ALTPCIE_PS_HIP_LOGIC parameter from 1 to 0 and recompile the design. 

    Depending on your design hierarchy, the PCIe IP register transfer level (RTL) source is typically located at:

    ./altera_pcie_a10_hip161/synth/*_altera_pcie_a10_hip_161_*.v

    Change from:

    localparam USE_ALTPCIE_RS_HIP_LOGIC = 1;

    to:

    localparam USE_ALTPCIE_RS_HIP_LOGIC = 0;

    Then, run a full compilation.

     

    Do not regenerate the PCIe IP core after changing this parameter. Regeneration overwrites the change.

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 17.0.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs