Article ID: 000077275 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Are there any known issues with the power estimation for input parallel on chip termination in the Stratix III Early Power Estimator version 7.1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, the Stratix® III Early Power Estimator (EPE) version 7.1 incorrectly models the power when using dynamic parallel on chip termination (OCT).  The power model assumes the parallel OCT is always on, regardless of the value entered in the output enable percentage column.  The power estimation will be larger than expected since the power calculation will include parallel OCT even when the output is driving.  In Stratix III devices, parallel OCT is disabled when a bidirectional pin is performing output functions.

    Resolution

    Version 7.2 of the Stratix III EPE uses the output enable percentage value when calculating the power consumed by parallel OCT for bidirectional pins.

    Related Products

    This article applies to 1 products

    Stratix® III FPGAs