Critical Issue
Description
When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants , the o_sclk signal is an asynchronous pulse routed through clock network. Timing Analyzer incorrectly identifies the o_sclk signal as a clock source and reports it as an unconstrained clock.
Resolution
No workaround is required, you can safely ignore this Timing Analyzer analysis of o_sclk as an unconstrained clock.