The following critical warning might appear when you use the ALTDDIO_IN Intel FPGA IP to implement a non-memory interface in a Cyclone® III or Cyclone® IV device and if the pin locations are not properly constrained.
Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os
Info: DQ capture register <name> at <location> is not assigned to the adjacent LAB of the corresponding DQ I/O <name> at <location>
Since no more than two global clocks (inverted clocks are counted separate from non-inverted clocks) may feed a LAB, the warning would appear if the adjacent LAB of the corresponding DQ I/O is already used by DDIO input registers for other pins.
The effect of the warning is increased skew. For a non-memory interface, it should be safe to ignore this warning as long as your timing requirements are met. If timing requirements are not met, you need to change the pin locations to fix this critical warning.