Article ID: 000076262 Content Type: Error Messages Last Reviewed: 08/14/2014

Error: Output port DATAOUT on atom “dqs_in_delay_1” which is a arriav_delay_chain primitive, is not connected to a valid destination

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see the above synthesis error when compiling an Arria® V DDR3 soft controller design created with Qsys in the Quartus® II software version 13.0 or later. The error occurs when logic inside the DDR3 controller is optimized away because the Avalon signals were not properly connected to an Avalon Master and an Avalon Master clock source.

    Resolution

    Make sure the Avalon interface is properly connected to an Avalon Master and an Avalon Master clock source.

    Related Products

    This article applies to 6 products

    Arria® V FPGAs and SoC FPGAs
    Arria® V GX FPGA
    Arria® V GT FPGA
    Arria® V GZ FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA