You may see this error in the Quartus® II software if you use a PLL to derive the input clock frequency to the ALTTEMP_SENSE mega function.
The input frequency applied to the internal temperature sensor must be less than or equal to 1.0MHz. A clock divider is available in the ALTTEMP_SENSE mega function to reduce your input clock to meet this requirement. For more details, please refer to the Temperature Sensor (ALTTEMP_SENSE) Megafunction User Guide (PDF).
The rounding nature of the PLL multiply and divide parameters may result in the actual output clock not being exact. If not using the clock divider, the resulting clock frequency could be higher than the required 1.0MHz. If using the clock divider, the resulting clock frequency could be higher than 40.0MHz or 80.0MHz, depending on the setting used for the clock divider.
To avoid this warning, revise the PLL parameters to make the rounded output clock's frequency less than or equal to 1.0MHz if not using the clock divider. If using the clock divider, revise the PLL parameters to make the rounded output clock's frequency less than or equal to 40.0MHz or 80.0MHz, depending on the setting used for the clock divider.