Article ID: 000075834 Content Type: Troubleshooting Last Reviewed: 08/23/2012

Why does Dynamic Phase Shift PLL reconfiguration fail when using the Altera PLL Reconfig megafunction on Stratix V and Arria V devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Altera® PLL Reconfig megafunction for Dynamic Phase Shift, reconfiguration will not occur if the Start register is written immediately after the Dynamic Phase Shift register is written.  This will be evident because the waitrequest signal on the Avalon-MM interface will not be asserted.

    This is due to a bug in the megafunction which will be fixed in a future version of the Quartus® II software.

    Resolution

    To ensure reconfiguration takes place, there must be at least one mgmt_clk cycle between the first write to the Dynamic_Phase_Shift register and the write to the start register.

    For more details on the operation of the Altera PLL reconfig MegaFunction, refer to AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions (PDF).

    Related Products

    This article applies to 6 products

    Stratix® V E FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Stratix® V GX FPGA