Article ID: 000075792 Content Type: Troubleshooting Last Reviewed: 05/09/2023

Why does programming the flash memory fail on the Stratix® V FPGA Development Kit?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The examples provided in the "Creating Flash Files Using the Nios® II EDS" section of the Stratix® V GX FPGA Development Kit User Guide are incorrect. They use an incorrect address for user hardware 1. 

    The Address Range given for User hardware 1 in Table A-1 Byte Address Flash Memory Map is:

    0x020C.0000 to 0x0413.FFFF

    Resolution

    Use the following commands to generate flash files correctly:

    For .sof files:

    sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020C0000

    --pfl --optionbit=0x00030000 --programmingmode=PSr

    For .elf files:

    elf2flash --base=0x0 --end=0x0FFFFFFF --reset=0x071C0000 --input=<yourfile>_sw.elf

    --output=<yourfile>_sw.flash

    --boot=/components/altera_nios2/boot_loader_cfi.srec

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA