Article ID: 000075633 Content Type: Troubleshooting Last Reviewed: 12/30/2022

Why does the serdes_pll_locked signal of upper PCI* Express Hard IP of Intel® Cyclone® V devices does not lock?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with Intel® Quartus® prime Software, Intel® Cyclone® V device that include 6 transceiver channels and two PCIe* Hard IPs will see a problem where the upper PCIe* Hard IP's serdes_pll_locked signal is unable to lock. The lower PCIe Hard IP does not has this issue and is working correctly.

    Resolution

    To work around this problem, run the enable_rx_pma_direct.xml script on top of the Quartus-generated SOF file. 

    Run the script from the command line as shown below, download the .xml script from here and run it from the same directory as the Quartus project file (.qpf).

    quartus_asm -e <name_of_sof> -x enable_rx_pma_direct.xml

     

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs