Article ID: 000075516 Content Type: Troubleshooting Last Reviewed: 06/19/2023

Why does the L-/H-Tile Avalon® streaming IP for PCI Express generate an MSI interrupt when either the msi_enable bit of the MSI Message Control Register or the Bus Master Enable bit of the PCI Command Register are not asserted?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The L-/H-Tile Avalon® streaming IP for PCI Express does not check the status of either the MSI Enable bit of the MSI Message Control Register or the Bus Master Enable bit of the PCI Command Register, and will generate a single dword Memory Write TLP to signal a MSI interrupt on the PCI Express link every time that app_msi_req signal gets asserted.

    Resolution

    To work around this problem, the user application logic must validate the status of the MSI Enable and Bus Master Enable bits before asserting app_msi_req signal.

    This information has been added to the 2021.09.17 release of the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCI Express User Guide.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 GX FPGA