Article ID: 000075373 Content Type: Troubleshooting Last Reviewed: 01/13/2023

Why does simulation of the Intel® Stratix® 10 FPGA JESD204B IP design example fail when using the ModelSim SE version 10.5c?

Environment

  • Intel® Quartus® Prime Pro Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Simulation of the Intel® Stratix® 10 JESD204B design example generated in the Intel® Quartus® Prime Software version 17.1.1 or earlier might fail when simulating at a resolution of 1 ps usng the ModelSim SE version 10.5c.

    Resolution

    To work around this problem, remove the 1 ps resolution from the vsim command line by removing '-t ps' from the vsim command in the modelsim do file msim_setup.tcl.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1. 

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs