Article ID: 000075066 Content Type: Error Messages Last Reviewed: 04/11/2023

Internal Error: Sub-system: SUT, File: /quartus/neto/sut/sut_delay_util_helper.cpp, Line: 4158

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This error may be seen in the Quartus® II software versions 10.0 and 10.0 SP1 if you target a Cyclone® IV device and you enable the EDA Netlist Writer to generate a simulation netlist. This error is triggered when the Standard Delay Format Output file (.sdo) is generated.

To work around this problem, disable the EDA Netlist Writer from generating the (.sdo) file by following these steps:

  1. On the Assignments menu, select Settings.
  2. In the Setting dialog box, expand the EDA Tool Settings category.
  3. Click Simulation.
  4. Click More EDA Netlist Writer Settings.
  5. Select the option Generate netlist for functional simulation only.
  6. Change the setting to On.
Resolution

This problem is fixed beginning with the Intel® Quartus® II software version 10.1.

Related Products

This article applies to 2 products

Cyclone® IV GX FPGA
Cyclone® IV E FPGA