Article ID: 000074935 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Why is the outclk of Clock Control Block Intel ® FPGA IP (ALTCLKCTRL) not disabled when the ena input is de-asserted?

Environment

  • Intel® Quartus® Prime Standard Edition
  • ALTCLKCTRL Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this problem if the Clock Control Block Intel® FPGA IP (ALTCLKCTRL) is configured with "For external path" mode.

    This is because the ena input is not used internally in this mode.

    Resolution

    There is no workaround for this problem. 

    This information will be updated in a future version of the Clock Control Block (ALTCLKCTRL) IP Core User Guide.

    Related Products

    This article applies to 3 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs

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