Article ID: 000074405 Content Type: Troubleshooting Last Reviewed: 03/07/2014

Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not?

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Description GND pins that have bank designations in the pin-out files of Stratix® V, Arria® V or Cyclone® V devices are defined as Programming Ground pins. They should be treated like all other GND pins on the device.

Related Products

This article applies to 15 products

Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Stratix® V GT FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA