Article ID: 000074339 Content Type: Troubleshooting Last Reviewed: 05/15/2013

Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    DDR3 Hard Memory Controller (HMC) designs with 2 or more MPFE ports enabled may experience a lock-up condition on the Avalon bus when simulating with ModelSim® 10.1b or earlier. The avl_ready signal for each MPFE port will de-assert low and stay low forever causing the simulation to hang.

    Resolution The workaround for this issue is to use ModelSim AE 10.1d or ModelSim SE 10.1d.

    Related Products

    This article applies to 11 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V E FPGA
    Cyclone® V SX SoC FPGA