Article ID: 000074027 Content Type: Error Messages Last Reviewed: 12/13/2016

Error:18496 The Output <name> in pin location <name> (pad_<number>) is too close to PLL clock input pin (<name>) in pin location <name> (pad_<number>)

Environment

  • Intel® Quartus® Prime Standard Edition
  • All

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    Description

    Due to a problem in the Quartus® Prime software version 16.0 and earlier, you may see this fitter error when the MAX® 10 E144 package design is compiled on Windows OS with the following conditions:

    1. Connected PLL signal (non-PLL input clock signal) to PLL input clock pin

    2. Assigned output pin next to PLL input clock pin which is connected to PLL signal (non-PLL input clock signal)

    Resolution

    A patch is available to fix this problem in the Quartus Prime Standard edition software version 16.1. Download and install patch 0.01cb from the appropriate link below. Be sure to read the readme for additional information. 

     

    Download the Quartus Prime Standard software version 16.1 patch 0.01cb for Windows (.exe)

    Download the Quartus Prime Standard software version 16.1 patch 0.01cb Readme (.txt)

     

    This problem is fixed in Quartus Prime Standard software version 16.1 Update 2.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs