Power and Performance
Intel® Agilex™ Device Support
The v19.3 release of the Intel® Quartus® Prime Pro Edition Software provides the first support for the Intel® Agilex™ device family of FPGAs. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10nm process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance or up to 40% lower power.1
Continue seeing improvements in compile time for your Intel® FPGA designs compared to prior releases. Check out the Compile User Guide for additional tips on how to reduce compile times.
See a 33% compile time reduction when compared to Intel® Quartus® v18.1 for designs with high utilization.2
Intuitive Design Environment
Data-Centric User Interface
The Intel® Quartus® Prime Pro Edition Software user interface has been updated in v19.3 to create a more intuitive interface and modern look and feel, including wizards, reports, and analysis tools. But beyond this, the Intel® Quartus® Prime Software uses data gathered during the development and compilation process to provide:
- Advanced analysis tasks leveraging multiple tools/features
- Well defined paths for guided analyses
- Deeper insight combining insights from different analysis views
The Design Assistant is a productivity tool meant for novice and advanced users. The tool enables faster design closure by reducing the number of design iterations required and speeds every iteration with targeted sanity checks and guidance at every stage of the compilation process. Learn more about Design Assistant with the provided video.
Unified Debug Toolkit (Early Access)
There are many different toolkits in Intel® Quartus® Prime Pro Edition Software, but they all have a different look and feel. The Unified Debug Toolkit (UDTK) is addressing this disparity. In v19.3 there is an early access version of the UDTK that highlights the new framework and incorporates the various transceiver toolkits into this new framework. In future releases the UDTK will incorporate all the debug toolkits together to give you a common flow for more intuitive debug.
Reduced Development Effort
Incremental Compilation and ECO Flows
When coming to the end of the development your design may need some small changes to meet timing, but you don’t want to do a full recompile. Incremental compilation and ECO flows provide you a method for tweaking just the blocks you need with ECO compilation speedup of 5x – 10x.3
To meet the growing need for utilizing the flexibility of an FPGA for arithmetic acceleration, Intel is introducing Fractal Synthesis - a feature that enables Intel® Quartus® Prime Design Software to use FPGA resources in a highly efficient manner for arithmetic heavy designs with repeating dot product structures. Fractal Synthesis allows users to see an up to 25% TOPS improvement compared to regular Intel® Quartus® Prime Software flow.4 Check out Fractal Synthesis in action with this video.
- New 3D visualization in Global Signal Visualization report to aid in analyzing clock sector and clock routing usage and congestion.
- New Global Router Congestion Analysis Reports that enable users to see a detailed view of which nets contribute to routing congestion and help users debug routing issues earlier in the compile flow. Learn how to use the new global router congestion reports with the provided video.
Documentation and Support
Find technical documentation, videos, and training courses for Intel® Quartus®
Prime Design Software.
Product and Performance Information
This Comparison based on Intel® Agilex™ FPGA and SoC family vs. Intel® Stratix® 10 FPGA using simulation results and is subject to change. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications, and roadmaps.
Intel® technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors.
Benchmarks were done on a suite of 80 customer designs on an Intel® Stratix® 10 1S280 device with Linux 64 operating system. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit https://www.intel.sg/benchmarks.
Benchmarks were done on a suite of 28 designs on an Intel® Stratix® 10 1S280 device with Linux 64 operating system. Comparison is done between the baseline compile time and the ECO compile time after netlist changes (8 – 2000 depending on what was available for ECO changes). Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For general information about performance and benchmark results, visit http://www.intel.com/benchmarks.
Benchmarks were done on a suite of 40 customer designs on an Intel® Stratix® 10 1S280 device with Linux 64 operating system. Comparison is done between Fractal Synthesis enabled vs disabled in Intel® Quartus® Prime Pro Edition Software v19.1 Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit https://www.intel.sg/benchmarks.