The serial digital interface (SDI) II intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.
The SDI II IP core highlights the following new features:
IEEE encryption for functional simulation across a variety of tools
Dynamic generation of user simulation testbench that matches the IP configuration
Dynamic generation of design example that serves as common entity for simulation and hardware verification
The following video tutorials are available for you to learn about using this IP.
SDI II IP Step-by -Step Implementation Guide for an Intel® Arria® 10 Device (8 min)
This video demonstrates how to implement an SDI II IP core in an Intel Arria 10 device. You will be guided through step by step generation in Intel® Quartus® software for all necessary transceiver-related components and integration.
SDI II Dynamic TX Clock Switching Feature Implementation and Hardware Verification (4 min)
This video provides theory of operation and a demonstration of the implementation of the SDI II dynamic TX clock switching capability for Intel Arria 10 devices.