Intel® Stratix® 10 FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration: Advantages that are unmatched in the industry. Featuring the revolutionary Intel® Hyperflex™ FPGA Architecture and built on the Intel 14 nm Tri-Gate process, Intel® Stratix® 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.1

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Family Variants

Intel® Stratix® 10 GX FPGAs

Intel® Stratix® 10 GX FPGAs are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.

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Intel® Stratix® 10 SX SoC FPGAs

Intel® Stratix® 10 SX SoC FPGAs feature hard processor system with 64 bit quad-core ARM* Cortex-A53 processor available in all densities in addition to all the features of Intel® Stratix® 10 GX devices.

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Intel® Stratix® 10 TX FPGAs

Intel® Stratix® 10 TX FPGAs deliver the most advanced transceiver capabilities in the industry by combining H- and E- transceiver tiles. The E-tile provides dual-mode transceiver capabilities, allowing a single transceiver channel to operate up to 56 Gbps in PAM-4 mode or 30 Gbps in NRZ mode. Intel® Stratix® 10 TX FPGAs also support the other breakthrough innovations of the Stratix GX and SX variants.

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Intel® Stratix® 10 MX FPGAs

Intel® Stratix® 10 MX FPGAs combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Intel® Stratix® 10 MX FPGAs support both H- and E- transceiver tiles.

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Benefits

Intel® Stratix® 10 devices address the design challenges in next-generation, high-performance systems in wireline and wireless communications, computing, storage, military, broadcast, medical, and test and measurement end markets.

Highest Performance FPGAs & SoCs

  • Ground breaking Intel® Hyperflex™ FPGA Architecture delivering 2X the core performance gains.1
  • Up to 10 TFLOPS of single-precision floating-point DSP performance.
  • Quad-core 64 bit ARM* Cortex-A53 hard processor subsystem operating up to 1.5 GHz.

Lower Operating Expense

Leveraging Intel's leadership in process technology, Intel® Stratix® 10 devices offer the most power-efficient technologies:

  • Up to 70% lower power than prior-generation high-end FPGAs and SoCs.1
  • Up to 80 giga floating point operations per second (GFLOPS)/Watt of single-precision floating point power efficiency.
  • Quad-core ARM Cortex-A53 processor optimized for performance per watt.

Break Through the Bandwidth Barrier

Transceiver tiles (L-, H-, and E-tile) with data rates up to 56 Gbps that deliver 7X bandwidth vs. previous generation FPGAs.1

  • Dual-mode transceiver (E-tile) supports up to 56 Gbps PAM-4 and 30 Gbps NRZ.
  • Up to 144 full duplex transceivers in a single package.
  • Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube.
  • Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 2,666 Mbps.

Achieve the Highest Level of System Integration

  • Largest monolithic FPGA device with 5.5 million LEs.
  • Heterogeneous 3D SiP solutions including transceivers and other advanced components.
  • 64 bit quad-core ARM* Cortex-A53 to enable hardware virtualization, system management and monitoring capabilities, acceleration preprocessing, and more.

Features

Intel® Hyperflex™ FPGA Architecture

To address the challenges presented by next-generation systems, Intel® Stratix® 10 FPGAs and SoCs feature the new Intel® Hyperflex™ FPGA Architecture, which delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end FPGAs.1

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Heterogeneous 3D Integration

Intel® Stratix® 10 FPGAs and SoCs leverage heterogeneous 3D System-in-Package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package.

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Transceivers

Intel® Stratix® 10 FPGAs and SoCs deliver a new era of transceiver technology with the introduction of innovative heterogeneous 3D System-in-Package (SiP) transceivers.

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External Memory Interfaces

Intel® Stratix® 10 devices provide memory interface support, including serial and parallel interfaces.

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Secure Device Manager

The Intel® Stratix® 10 device family introduces a new Secure Device Manager (SDM) available in all densities and device family variants.

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DSP

With Intel® Stratix® 10 devices, digital signal processing (DSP) designs can achieve up to 10 tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.

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SEU Mitigation

Single-event upsets (SEUs) are rare, unintended changes in the state of internal memory elements caused by radiation effects.

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Hard Processor System

Building on Intel’s leadership in SoCs, Intel® Stratix® 10 SoCs include a next-generation hard processor system (HPS) to deliver the industry’s highest performance and most power-efficient SoCs.

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Design Tools

Compatible design tools deliver the highest performance, highest logic utilization, and fastest compile times for high-end FPGA designs.

Intel® Quartus® Prime Software

The Intel® Quartus® Prime Design Software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel® Quartus® Prime Software delivers the highest performance and productivity for Intel® FPGAs, CPLDs, and SoCs.

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Fast Forward Compile

Intel® Stratix® 10 FPGAs deliver a breakthrough leap in core performance. Users can now unlock design performance by taking advantage of the innovative capabilities of the  Intel® Hyperflex™ FPGA Architecture, reaching breakthrough levels of performance not possible in previous-generation FPGA architectures.

Intel® FPGA SDK for OpenCL™

Intel® FPGA SDK for OpenCL™ combines Open Computing Language (OpenCL™), an open standard parallel programming language, with the parallel performance capabilities of an FPGA to provide a powerful solution for system acceleration. 

OpenCL™ and the OpenCL™ logo are trademarks of Apple Inc. used by permission by Khronos.2

Applications

ASIC Prototyping

Higher productivity by reducing design partitioning complexity using monolithic FPGA fabric.

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Cyber Security

fMAX over 900 MHz allows monitoring of all supported protocols at line rates.

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Data Center Acceleration

Intel® Hyperflex™ FPGA Architecture delivers up to 1 GHz performance, enabling breakthroughs in computational throughput.

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Wireline

fMAX over 700 MHz using the Intel® Hyperflex™ FPGA Architecture enabling 400G Ethernet.

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Radar

Up to 10 TFLOPS of IEEE 754 compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power.

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OTN/Data Center Interconnect

Heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles delivers 30G backplane support with a path to 56G data rates.

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Videos

Intel® Stratix® 10 Device Demo Videos

28G Transceivers

In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers, connected via Intel's EMIB technology, operating at 28 Gbps backplane performance.

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Intel® Hyperflex™ Architecture

Intel® Hyperflex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the fMAX performance*. This video shows a side by side comparison of an original and Hyper-Optimized design.

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PCIe* Gen3 DMA to DDR4 SDRA

Intel® Stratix® 10 devices, which include PCIe* and memory controller hard IP blocks, when combined with Avalon® Memory Mapped and direct memory access functions, create a high-performance reference design.

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Documentation and Support


Find technical documentation, videos, and training courses for your Intel® Stratix® 10 designs.

Product and Performance Information

1

Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.sg/benchmarks.

2

OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.