Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 GX FPGA contains up to 10.2 million LEs. They also feature up to 96 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The transceivers are capable of up to 28.3 Gbps short reach and across the backplane. These devices are optimized for FPGA applications that require the highest transceiver bandwidth and core fabric performance.
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Intel® Stratix® 10 GX FPGA
Features and Benefits
First Intel® FPGA to Run on the Hyperflex™ FPGA Architecture
The Intel® Hyperflex™ FPGA Architecture introduces additional bypassable registers everywhere throughout the FPGA fabric. These additional registers, called Hyper-Registers, are available on every interconnect routing segment and at the inputs of all functional blocks. Hyper-Registers enable three key design techniques to achieve the 2X core performance increase: Hyper-Retiming to eliminate critical paths, Hyper-Pipelining to eliminate routing delays, and Hyper-Optimization to achieve the best performance.
Enabling Next-Generation Chiplets Using Intel’s 3D System-in-Package Technology
The patented Embedded Multi-Die Interconnect Bridge (EMIB) technology provides a simple integration flow and offers an ultra-high density interconnect between heterogeneous die in the same package. It also enables in-package functionality that was either too complex or too cost prohibitive to implement with alternative in-package integration solutions.
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