Video and Image Processing Suite

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs. These Intel FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, smart city/retail, and consumer.

Video and Image Processing Suite User Guide ›

Video and Image Processing Suite

Video and Image Processing Suite Intel FPGA IP Functions

Intel FPGA IP Function


2D FIR Filter II

Implements a 3x3, 5x5, or 7x7 finite impulse response (FIR) filter on an image data stream to smooth or sharpen images.

Alpha Blending Mixer and Mixer II

Mixes and blends multiple image streams—useful for implementing text overlay and picture-in-picture mixing.

Avalon-ST Video Monitor

Captures video data packets without adding additional delays and connect to trace system IP for collecting video trace data.

Avalon-ST Video Stream Cleaner

Removes and repairs the non-ideal sequences and error cases
present in the incoming data stream to produce an output stream that complies with the implicit ideal use model.

Chroma Resampler II

Changes the sampling rate of the chroma data for image frames, for example from 4:2:2 to 4:4:4 or 4:2:2 to 4:2:0.

Clipper II

Provide a way to clip video streams and can be configured at compile time or at run time.

Clocked Video Input (CVI), Clocked Video Input II (CVI II), Clocked Video Output (CVO) and Clocked Video Output II (CVO II)

The Clocked Video Interface IP cores convert clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST video; and vice versa.

Color Plane Sequencer II

Changes how color plane samples are transmitted across the Avalon-ST interface. This function can be used to split and join video streams, giving control over the routing of color plane samples.

Color Space Converter II (CSC II)

Convert image data between a variety of different color spaces such as RGB to YCrCb.

Configurable Guard Bands

The Configurable Guard Bands IP core compares each color plane in the input video stream to upper and lower guard bands values.

Control Synchronizer

Synchronizes the changes made to the video stream in real time between two functions.

Deinterlacer II

Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm. Also supports "bob" and "weave" algorithms, low-angle edge detection, 3:2 cadence detection, and low latency.

Frame Buffer II

Buffer video frames into external RAM. This core supports double or triple-buffering with a range of options for frame dropping and repeating.

Frame Reader II

Reads video from external memory and outputs it as a stream.

Gamma Corrector II

Allows video streams to be corrected for the physical properties of display devices.

Interlacer II

Converts progressive video to interlaced video by dropping half the lines of incoming progressive frames.

Scaler II

HDL code-based Scaler II Intel FPGA IP function uses less area than first-generation Scaler in the Video and Image Processing Suite while delivering higher performance. The Scaler II function further reduces required resources with new support of 4:2:2 chroma data sampling rate. Both linear and polyphase algorithms are available with new feature of edge adaptive algorithm to reduce blurriness while maintaining realism.

Switch II

Allow video streams to be switched in real time.

Test Pattern Generator II

Generate a video stream that contains still color bars for use as a test pattern.

Trace System

Monitors captured data from video monitor and connects to host System Console via JTAG or USB for display

Design Examples and Development Kits

The following design examples are available for you to run on the development kits.

IP Quality Metrics


Year IP was first released


Latest version of Intel® Quartus® software supported





Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*-Intel® FPGA Edition

    Timing and/or layout constraints

    Testbench or design example

    Documentation with revision control

    Readme file







Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP core is enabled for Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided

sw.tcl file

Driver operating system (OS) support



User interface

Clocked Video (into Clocked Video Input and out of Clocked Video Output), Avalon®-ST (all other datapaths)

IP-XACT metadata



Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Arria® II GX/GZ, Arria® V, Intel® Arria® 10, Cyclone® IV ES/GX, Cyclone® V, Intel® Cyclone® 10, Intel® MAX® 10, Stratix® IV, Stratix® V

Industry standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Intel Arria 10, Intel Cyclone 10

Interoperability reports available