Product and Performance Information
See backup for workloads and configurations. Results may vary. For more complete information about performance and benchmark results, visit intel.com/benchmarks.
Each Intel® Agilex™ FPGA DSP block can perform two FP16 floating-point operations (FLOPs) per clock cycle. Total FLOPs for FP16 configuration is derived by multiplying 2x the maximum number of DSP blocks to be offered in a single Intel® Agilex™ FPGA by the maximum clock frequency that will be specified for that block.