GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 3.0.0

This document provides features, usage guidelines, and functional description of the GTS Serial Lite IV Intel® FPGA IP design examples using transceivers in Agilex™ 5 devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during system level design planning phase.
  • Hardware designers when integrating the IP into their system level design.
  • Validation engineers during system level simulation and hardware validation phase.

Related Documents

For other documents related to the GTS Serial Lite IV Intel® FPGA IP, refer to the related information.

Acronyms and Glossary

Table 1.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface
Related Information
Level Two Title