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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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4.3. Nios® V Processor Booting Methods
There are a few methods to boot up the Nios® V processor in Intel FPGA devices. The methods to boot up Nios® V processor vary according to the flash memory selection and device families.
Supported Boot Memories | Device | Nios® V Processor Booting Methods | Application Runtime Location | Boot Copier |
---|---|---|---|---|
Configuration QSPI Flash (for Active Serial configuration) | Control block-based devices (with Generic Serial Flash Interface Intel FPGA IP) 2 | Nios® V processor application execute-in-place from configuration QSPI flash |
Configuration QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections) | alt_load() function |
Nios® V processor application copied from configuration QSPI flash to RAM using boot copier | OCRAM/ External RAM | GSFI bootloader | ||
SDM-based devices (with Mailbox Client Intel FPGA IP). 2 | Nios® V processor application copied from configuration QSPI flash to RAM using boot copier | OCRAM/ External RAM | SDM bootloader | |
On-chip Memory (OCRAM) |
All supported Intel® FPGA devices 2 | Nios® V processor application execute-in-place from OCRAM | OCRAM | alt_load() function |
Tightly Coupled Memory (TCM) | All supported Intel® FPGA devices2 | Nios® V processor application execute-in-place from TCM | Instruction TCM (XIP) + Data TCM (for writable data sections) | None |
Figure 13. Nios® V Processor Boot Flow